Rakesh Kumar

208 Coordinated Science Laboratory
1308 West Main Street
Urbana, IL 61801
Email: rakeshk@illinois.edu

Rakesh Kumar is an Associate Professor in the Electrical and Computer Engineering Department at the University of Illinois at Urbana Champaign and a Co-Founder and Chief Architect at Hyperion Core, Inc. His current research interests are in computer architecture, low power and error resilient computer systems, and approximate computing.

His most significant research contributions are in the areas of multi-core architecture and design (his past research on heterogeneous multi-core architectures and conjoined-core architectures has directly influenced processor products and roadmaps from several companies), peak power management (he co-developed the first techniques for peak power management for single-core and multi-core processors), stochastic and approximate computing (he co-developed the first set of techniques for graceful voltage-reliability tradeoffs in hardware and functional units; he also co-developed the concept of recovery-driven design), algorithm-based fault tolerance (he co-developed the first ABFT techniques targeting sparse algebra; he also led the development of several algorithmic techniques to build error tolerant versions of applications), low power computing (he introduced techniques such as software canaries, power-balanced pipelines, and correction prediction), and memory systems for high performance computing (he developed several novel techniques for reducing the power cost of building reliable memory systems). The research contributions have been covered by news outlets as varied as BBC, HPCWire, IEEE Spectrum, and Slashdot.

His research recognitions include several best paper awards and best paper award nominations, ARO Young Investigator Award, Arnold O Beckman Research Award, FAA Creative Research Award, UCSD CSE Best Dissertation Award, and an IBM PhD Fellowship. Teaching recognitions include Ronald W Pratt Faculty Outstanding Teaching Award and multiple appearances on UIUC's List of Teachers Ranked as Excellent. Advising recognitions include Engineering Council Outstanding Advisor Award.

In addition to his academic responsibilities and responsibilities to his startup company, Rakesh frequently consults with technology and IP companies on issues related to computer architecture and memories and also works with law firms as a subject matter expert or as an expert witness.

Rakesh has a BS from IIT Kharagpur and a PhD from University of California at San Diego.

Current Research

Low Power Computing (HPCA15, ISLPED14, HPCA12, MICRO09..)
Approximate Computing (ICCD14, ICCAD13, ICCAD12, DSN12, DAC12, DAC10, CASES11, DSN10, DATE10, HPCA10, ASPDAC10..)
Memory Systems (HPCA16, SC14, SC13, HPCA13..)

Recent Publications

Parity Helix: Efficient Protection for Single-Dimensional Faults in Multi-dimensional Memory Systems, HPCA 2016, (PDF).
Correction Prediction: Reducing Error Correction Latency for On-Chip Memories, HPCA 2015, (PDF).
(an earlier version selected as a Best Paper at SRC TECHCON 2014).
ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems, SC 2014, (PDF).
Software Canaries: Software-based Path Delay Fault Testing for Variation-aware Energy-efficient Design, ISLPED 2014, (PDF).
Markov Chain Algorithms: A Template for Building Future Robust Low Power Systems, Asilomar 2013, (PDF).
Low Power, Low Storage Overhead Chipkill Correct via Multi-Line Error Correction (Multi-ECC), SC 2013, (PDF)
(an earlier version selected as the Best of IEEE Computer Architecture Letters 2013).
On Reconfiguration-Oriented Approximate Adder Design and Its Application,ICCAD 2013, (PDF).
An Algorithmic Approach to Error Localization and Partial Recomputation for Low-Overhead Fault Tolerance on Parallel Systems, DSN 2013, (PDF).
Adaptive Reliability Chipkill Correct (ARCC), HPCA 2013, (PDF).
On Logic Synthesis for Timing Speculation, ICCAD 2012, (PDF).
Algorithmic Approaches to Low Overhead Fault Detection for Sparse Linear Algebra, DSN 2012, (PDF)
(an earlier version selected as a Best Paper at SRC TECHCON 2011).
Compiling for Energy Efficiency on Timing Speculative Processors, DAC 2012, (PDF).
On Software Design for Stochastic Processors, DAC 2012, (PDF). (invited)
Power-Balanced Pipelines, HPCA 2012, (PDF). (Nominated for Best Paper Award).
Architecting Processors to Allow Voltage/Reliability Tradeoffs. CASES 2011. (
PDF). (Best Paper Award).
On the Efficacy of NBTI Mitigation Techniques, DATE 2011, (PDF).
MOPED: Orchestrating Interprocess Message Data on CMPs, HPCA 2011, (PDF).
A Numerical Optimization-based Methodology for Application Robustification: Transforming Applications for Error Tolerance, DSN 2010, (PDF).
Recovery-driven Design: A Methodology for Power Minimization for Error Tolerant Processor Modules, DAC 2010, (PDF).
Stochastic Computation, DAC 2010, (PDF) (invited).
Scalable Stochastic Processors", DATE 2010, (PDF).
Designing Processors from the Ground Up to Allow Voltage/Reliability Tradeoffs, HPCA 2010, (PDF).
Slack Redistribution for Graceful Degradation Under Voltage Overscaling. ASPDAC 2010, (PDF).
Reducing Peak Power with a Table-Driven Adaptive Processor Core, MICRO 2009, (PDF).


Current PhD Students

Henry Duwe (Low Power Processors and Caches)
Xun (Stevenson) Jian (Memory Systems for Data Centers and Supercomputers)
Aakash Modi (Heterogeneous Systems)
Matthew Tomei (Extreme Energy Efficiency)
Weidong Ye (Embedded Systems)

PhD Alums

John Sartori (First Employment: Assistant Professor, EE Department, University of Minnesota)
Joseph Sloan (First Employment: Assistant Professor, EE Department, University of Texas at Dallas)


DARPA, DOE, NSF, SRC, NSA, ARO, Intel, AMD, Oracle, Cisco